Hi ,

I work in EMIR methodology. I am interested in learning STA but not getting an opportunity. What should i do ? My managers think if i learn STA i will switch the company. Because of this they are not allowing me to

Hi,

Can anyone share some info about renesas india, like work culture, layoffs, annual compensation (average).

I have got an offer from renesas hyderabad, hence asking. I am currently at TI.

Hi everyone,

I graduated with a degree in Electronics Engineering (ECE) from a university in the Philippines last year. Immediately after graduation, I accepted a research role at my university. For the past year, I have been working as a Project Technical Assistant IV. My role primarily involves 3D modeling, basic PCB design, technical paper writing, and presenting our work at tech expos.

While I appreciate the research experience, my true passion is Chip Design (IC Design). However, as a beginner, I am feeling a bit overwhelmed and confused about the correct roadmap.

I have started taking some basic Verilog courses, but I have a few critical questions for the industry veterans here:

1. Prerequisites: Am I missing anything? Do I need to review specific topics (like Digital Logic Design or Computer Architecture) before diving deeper into Hardware Description Languages (HDLs)?
2. Verilog vs. SystemVerilog: I recently read that SystemVerilog is the current industry standard. Should I skip Verilog entirely and go straight to SystemVerilog, or is a foundation in Verilog necessary first?
3. Beyond HDLs: What other core concepts, fundamentals, or methodologies (e.g., Verification, Synthesis, Static Timing Analysis) do I need to learn to be job-ready?
4. EDA Tools: Which Electronic Design Automation (EDA) tools should a beginner familiarize themselves with? Are there open-source alternatives (like OpenLane or ModelSim student editions) that are highly regarded?
5. Portfolio Projects: What are some beginner-to-intermediate Verilog/SystemVerilog projects that would actually stand out on a resume or job application?
6. Career Paths & Roles: What are the different roles available within the chip design industry, what specific skills are required for each, and which of these roles are most suitable/accessible for a recent graduate?

I am genuinely amazed by semiconductor engineering and thoroughly enjoy learning HDLs. In fact, I am planning to specialize in semiconductors if I pursue a Master's degree in the future.

Any guidance, learning roadmap recommendations, or advice on how to break into the industry from my current position would be immensely appreciated.

Thank you so much!

AI is improving fast and many startups as well as the big EDA providers are building systems for AI-based analog IC design and layout. What is the current state of those systems? What do they currently not quite succeed to do?

Can any of these take an English spec for a block and build schematic, layout and routing with associated test benches and verification all the way to a design ready for tapeout? (Not just finding parameters to a pre-existing layout generator for a specific block type.) If so, how complex blocks can they do?

Context: I'm 22, joined one of the big players in AI hardware about 4 months back. First job right after bachelors.

I studied traditional CPU architecture during college and knew nothing about AI accelerators. During these 4 months, I have been working mainly on roofline modelling and performance analysis, nothing related to deep microarch yet.

I feel i have developed some intuition about how performance modelling works and how to analyse workloads, bottlenecks at the system level, and how LLMs behave with the given hardware (with different shardings and their implications).

My manager asked me whether I want to work on a problem statemen related to microarch. Just wanted your opinion on should I keep working on performance for now, or should I pick something related to microarch?

Also, in general for an architect, would you recommend performance or microarch as the primary area of specialization in the long run?

What will be the salary that can be asked for a 5 YOE RTL design engineer with a current package of 22LPA, who got an offer in Intel ?

Is it good to move to Intel ? (As layoffs are happening )

Work - Life balance in Intel ?

Hi all

I started my career at Synopsys doing .lib characterization, but unfortunately got laid off. I joined another company after that, but they got acquired and my role became redundant, so I'm currently without a job. I've been giving interviews for Physical Design roles since I have past internship experience in it and feel it's a better profile, but I haven't had any luck yet. Can anyone guide me on what I should do next?

Also i will be very happy if someone has any openings for me.

My exp

Mtech from NIT

Intel intern

Then synopsys

Then Eximietas

Total 3.5 yes including internship

Thanks 😊

I'm wondering how the temperature sensor chip would characterize/trim the temperature coefficient of the system for mass production. Can you do two temperature point measurement for all of the chip at package level? Or you do it at wafer level? Do you measure every die/package or just one chip to represent the whole lot.
From what I understand, it takes time to heat up the environment, so doing two point measurement for every package is expensive. Not sure how it is done for temperature sensor that requires good accuracy.

Hi guys,

27F, working in MNC as Physical Design engineer from last 3+ years. I want to move to Europe or UK.

I have applied directly for couple of jobs but didn't get any call back.

Are the opportunities in Europe less for Indians? What is the best possible way I can move to Europe? Internal transfer might take 2 years from now and that too not sure if my company allows it.

Please help me with these queries.

512-bit multiplication · 2.61 million AND gates · 26.71 seconds · Independently checked 512-bit PAC certificate

In my previous post, I shared Parat v1.3 and its independently checkable proof for a 256-bit Yosys Booth multiplier. Since then, I have tested larger multiplier circuits and expanded the SAT benchmark suite.

512-bit multiplier: 26.71 seconds

I generated an unsigned 512×512-bit multiplier using carry-save compression followed by a final ripple adder.

The generated circuit contains:

• 2,614,272 AND gates
• 1,024 primary inputs and 1,024 output bits
• An approximately 59 MB ASCII AIGER file

Parat returned CORRECT MULTIPLIER in 26.71 seconds, with approximately 2.27 GB peak resident memory.

An independent bit-parallel simulator checked 64 operand pairs against exact integer multiplication. Every output bit matched.

A separate 512-bit Wallace multiplier: PAC certificate

I also have results from a separate 512-bit Wallace multiplier circuit, containing approximately 2.63 million AND gates.

For that circuit:

• PAC certificate generation took approximately 5–5.5 minutes.
• Independent verification with pacheck2 took approximately 2.5 minutes.
• The recorded proof file was approximately 2.18 GB, with about 122 MB of polynomial data and 43 MB of specification data.

These are separate circuit experiments: the 26.71-second result above is for the carry-save/ripple architecture, while the independently checked PAC certificate belongs to the Wallace-circuit experiment.

Fault-injection testing

I modified individual gates in copies of the 512-bit carry-save/ripple circuit.

Three tested mutations—including an output-bit mutation, an early partial-product gate mutation and a near-final gate mutation—were detected as incorrect.

One middle-compressor-gate mutation did not produce a verdict within approximately 120 seconds. That case remains unresolved; the original correct circuit did return CORRECT MULTIPLIER.

Broader SAT benchmarks

On the tested Linux build:

I also tested 176 SAT Competition 2005 industrial instances with a 10-second limit per instance. 142 SAT models were independently validated; 34 instances timed out.

For the UUF sets, reported UNSAT statuses matched expected results, but those results have not all been independently checked with proof certificates.

Limitations

The 26.71-second result applies to one generated circuit, not every multiplier architecture. One middle-gate mutation remains unresolved, and 34 industrial cases exceeded the time limit. Results from separate circuits should not be treated as if they came from one identical netlist.

Repository: https://github.com/himanshu161106-crypto/parat

The code was written by AI under my direction. The project ideas, mathematical approach, experiment design and testing were mine.

I'd appreciate technical feedback on improving the difficult middle-gate case and on additional large multiplier architectures worth testing.

As mentioned, looking for a mentor who could advise me regarding some important decisions I'm about to take. I'm 28, working in chip industry for 4 yrs in Bangalore, India. Would love to discuss and practical suggestions from someone veteran or even mid career stage professionals. Please comment down or DM! Would appreciate your help!.

Is this low ball offer ?

I am having a group project that is design and simulation of all digital pll in 22nm FDX. I am responsible to do the TDC.

The goal is to minimize random jitter below 200fs.

Output freq from 9 to 11Ghz.

There is also a spec on vco phase noise and settling time for loop.

1-I am a bit confused how to start should we do a linear model or time domain model first?

2-We studied Sam Palermo lectures for pll and adpll, if there is suggestions for good books about adpll that can make us understand system better please tell us about.

I’m trying to design an LNA that meets certain specs. So for the first part, as per my course guidelines, I tried to find Jopt which provides NFmin.

Now, I tried to find the width that gives me Ropt at 50ohms. I’ve a 1u cmos width and I’m sweeping the Number of fingers trying to see where it lands at 50ohms. I have placed an idea current source that provides the current proportional with the Jopt I found in part 1.

My problem is here. I’m finding the number of fingers to be >200 to have Ropt at 50 and also my NFmin is shooting up as well(20dBs). I’m not sure where I’m going wrong. If you have any idea or suggestion please share. I’m new to cadence and find the whole thing overwhelming.

Unfortunately I’m making the post away from my pc and couldn’t post the schematic

I’m working at NVIDIA India with more than 3 years of experience. My fixed pay is ₹22LPA, and I’m from one of the top engineering colleges in India.
Is this compensation competitive for my experience? What fixed salary range should I expect at a similar level in AMD, Qualcomm, Apple, Google or other semiconductor companies in India?
Looking for honest opinions, preferably from people in the industry.

Hi everyone!

I recently received an email from Meta to schedule an HR call for the ASIC Engineer Intern, Design role. The meeting is scheduled for around 30 minutes, and I believe this is the initial HR screening or phone screening round.

Since this is my first HR round with Meta, I wanted to ask people who have gone through this process or have experience with Meta hardware/ASIC internship interviews:

• What should I expect during this 30-minute call?
• Is it primarily about my resume, projects, motivation for joining Meta, and availability, or should I also prepare for technical questions?
• What kind of questions do recruiters generally ask for ASIC Design internship roles?
• Do they discuss location preferences, internship duration, compensation, or the next interview rounds?
• Are there any specific things I should prepare beforehand?

I would really appreciate any insights from people who have interviewed with Meta for similar hardware, ASIC, or silicon engineering internship roles.

Thanks in advance for your help!

I’ve been invited to a hirevue for a graduate GPU modelling role at Arm (Trondheim). It’s 3 video questions, 1 written response and 1 coding challenge, about an hour in total.

1. Has anyone done an Arm HireVue recently, especially for graduate GPU related role?
2. What level is the coding challenge? LeetCode easy/medium, or more C++/systems-specific?
3. Were the video questions mostly behavioural, or did any get technical (architecture, CPUs or GPUs)?

My background is GPU performance (CUDA, profiling) and computer architecture (I built an out-of-order CPU simulator in C++), so any pointers on what to brush up on would be really appreciated.

Hey all, I'm the lookout for field applications engineering eda roles. If anyone is willing to refer please dm. I have over 2.5 years of work ex in analog layout design and want to transition to field applications engineer role. Location preference : anywhere in India

Hi guys, I'm curious if anyone here has experience running a service business in chip design or EDA. I'm trying to figure out what skills are worth learning if I want to sell services to companies in this industry, either as a freelancer or by building a small business around a specific service. I've heard that it is very much about trust and connections, so I'm wondering how realistic it is to get started without an existing network. Could you start on Upwork, build a portfolio, and use LinkedIn/email/? to find clients, or is that not really how things work.

For those of you who have done this, I'd love to know:

What services have you actually sold, and who were your clients?

What skills would you focus on learning if you were starting today?

Are there things semiconductor startups commonly outsource instead of hiring someone full-time?

How did you get your first clients?

Honestly, is this worth pursuing, or is it too difficult to break into without connections?

Thanks a lot!

Looks like FDSOI has not gained much traction on this front. Not too many fabless companies are adopting this technology except for automotive applications. Is it because the methodology for large scale digital design is not formalized yet. For example, dynamic body biasing which is the main incentive of this tech. The foundries do have core libraries with discrete Vt but not sure if fits in within the current methodology, They are claiming this is the next frontier for physical AI chips, but as far as I know EDA and fabless companies are not showing much interest. Any thoughts?

After upgrading from Xcelium 24.03 to a release at or after 24.09, I see a change in the SDF annotation statistics. The option -sdf_splitvlog_setuphold appears to be the default now and when I use it in newest versions, I see a warning that this option is deprecated. As far as I can tell, there is no documented option to get the old behavior back.

What I see

My design uses only combined $setuphold timing checks in the specify block, and the SDF has combined SETUPHOLD entries as well. With -scopewise_sdfstats_log, the statistics table now also lists $setup and $hold as separate rows below $setuphold. In 24.03 only the combined $setuphold row was shown.

Minimal reproducer

design.sv:

module dut (input clk, input d, output reg q);
  always @(posedge clk) q <= d;

  specify
    (clk *> q) = (1.0, 1.0);
    $setuphold(posedge clk, d, 0.1, 0.1);
  endspecify
endmodule

test.sdf:

(DELAYFILE
  (SDFVERSION "2.1")
  (DESIGN "dut")
  (DATE "2026-10-14")
  (VENDOR "Example")
  (PROGRAM "Custom")
  (VERSION "1.0")
  (DIVIDER /)
  (VOLTAGE 1.0)
  (PROCESS "typ")
  (TEMPERATURE 25.0)
  (CELL
    (CELLTYPE "dut")
    (INSTANCE)
    (DELAY
      (ABSOLUTE
        (IOPATH clk q (1.0:1.0:1.0) (1.0:1.0:1.0))
      )
    )
    (TIMINGCHECK
      (SETUPHOLD d (posedge clk)
        (0.1:0.1:0.1)
        (0.1:0.1:0.1)
      )
    )
  )
)

sdf.cmd:

SDF_FILE          = "test.sdf",
SCOPE             = tb.u_dut,
LOG_FILE          = "sdf_annotation.log",
MTM_CONTROL       = "TYPICAL";

testbench.sv:

module tb;
  reg clk = 0;
  reg d = 0;
  wire q;

  dut u_dut (.clk(clk), .d(d), .q(q));

  initial begin
    #10 clk = 1; #10 clk = 0;
    #10 d = 1;
    #10 clk = 1; #10 clk = 0;
    #50 $finish;
  end
endmodule

Compile options: -timescale 1ns/1ps -sysv -sdf_cmd_file sdf.cmd -scopewise_sdfstats_log /dev/stdout

Resulting output (relevant part)

Path Delays   1   0   1   100.00
$setuphold    1   0.00   1.00   100.00
      $setup  1   0   1   100.00
       $hold  1   0   1   100.00

The summary lines still say No. of Tchecks = 1, and annotation is 100%. So I assume this is only a change in the report format and not in simulation behavior. Please correct me if that is wrong.

Question

Is there a documented (or undocumented) option or setting in the current releases that restores the old reporting/behavior, with combined $setuphold line and no $setup/$hold breakdown (even when I use combined $setuphold both in the .sdf and in the RTL files)?

Basically what the title says, would love to know if their architecture/compiler technology seems promising and if they can make it out of the seed round

Anyone in the process of Nvidia & Meta DV 2027!?